Manufacture of trench-gate semiconductor devices

ABSTRACT

A method of manufacturing a trench-gate semiconductor device ( 1 ), the method including forming trenches ( 20 ) in a semiconductor body ( 10 ) in an active transistor cell area of the device, the trenches ( 20 ) each having a trench bottom and trench sidewalls, and providing silicon oxide gate insulation ( 21 ) in the trenches such that the gate insulation ( 33 ) at the trench bottoms is thicker than the gate insulation ( 21 ) at the trench sidewalls in order to reduce the gate-drain capacitance of the device. The method includes, after forming the trenches ( 20 ), the steps of: (a) forming a silicon oxide layer ( 21 ) at the trench bottoms and trench sidewalls; (b) depositing a layer of doped polysilicon ( 31 ) adjacent the trench bottoms and trench side walls; (c) forming silicon nitride spacers ( 32 ) on the doped polysilicon ( 21 ) adjacent the trench sidewalls leaving the doped polysilicon exposed at the trench bottoms; (d) thermally oxidising the exposed doped polysilicon to grow said thicker gate insulation ( 33 ) at the trench bottoms; (e) removing the silicon nitride spacers ( 32 ); and (f) depositing gate conductive material ( 34 ) within the trenches to form a gate electrode for the device. The final thickness of the thicker gate insulation ( 33 ) at the trench bottoms is well controlled by the thickness of the layer of doped polysilicon ( 31 ) deposited in step (b). Also the doped (preferably greater than 5 e 19 cm-3) polysilicon oxidises fast at low temperatures (preferably 700-800° C.), reducing the risk of diffusing (e.g. p body) implantations present in the device at that stage.

The present invention relates to methods of manufacturing trench-gatesemiconductor devices.

FIG. 1 of the accompanying drawings show a schematic cross-section viewof a known trench-gate form of vertical MOSFET power transistorsemiconductor device. The device 1 comprises a silicon semiconductorbody with top and bottom major surfaces 10 a, 10 b, a first conductivitytype drain region 11 and a first conductivity type drain drift region 12is FIG. 1 shows the lateral extent (the cell pitch) of one completetransistor cell TC and part of an adjacent transistor cell at eitherside of the cell TC. Two sections are shown of a peripheral insulatedgate structure G located in a trench 20 at the boundary between each twoadjacent transistor cells. The trench-gate structure G extendsvertically through a channel-accommodating second, opposite,conductivity, type body region 23 into the drain drift region 12, andhas silicon oxide gate insulation 21A, 21B respectively at the sidewalls and at the bottom of the trench 20 and conductive gate material 22in the trench 20 within the gate insulation 21A, 21B. A source region24, of the first conductivity type, is present in each transistor cellunder the top major surface 10 a and adjacent the trench gate 21A, 21B,22. Thus the source region 24 and the drain drift region 12 arevertically separated by the channel-accommodating body region 23adjacent the side walls of the trench-gate provided by the peripheralinsulated gate structure G. This enables a vertical conduction channel23 a to be formed in the body portion 23 adjacent the side wall gateinsulation 21A when a suitable gate potential is applied to the gatematerial 22 in the on-state of the device 1, whereby current flows in apath in each transistor cell from the source region 24 verticallythrough the conduction channel 23 a to the drain drift region 12.

An insulating region 25 is provided over the gate structure G. Sourcemetallisation 18 contacting all of the source regions 24 is provided onthe first major surface 10a over the insulating region 25 to provide asource electrode S. Although not shown, electrical connection to theinsulated gate structure G is provided by extending the side wall gateinsulation 21A from the trenches 20 on to the top surface 10a of thesemiconductor body 10 in an inactive area outside the active transistorcell area and extending the gate material 22 on to this top surfaceinsulating layer where it is contacted by metallisation to provide agate electrode. A metallisation layer 19 forms an ohmic contact with thedrain region 11 so as to provide a drain electrode D.

The cross-section view shown in FIG. 1 applies equally to each of twocell geometries which are known for trench-gate devices. FIG. 2 of theaccompanying drawings shows a plan view of an open-cell geometry havinga one-dimensionally repetitive pattern in which the trench-gates G1 areparallel stripes which each extend across the active area of the deviceat the peripheries of open stripe-shaped transistor cells TC1. In thiscase FIG. 1 shows a cross-section view along the line II-II of FIG. 2.FIG. 3 of the accompanying drawings shows a plan view of a closed-cellgeometry having a two-dimensionally repetitive pattern in which thetrench-gate structure G over the active area of the device surroundsclosed polygonal transistor cells TC2 and comprises a trench networkincluding segment trench regions G2S adjacent sides of the transistorcells TC2 and intersection trench regions G21 adjacent corners of thetransistor cells TC2. In this case FIG. 1 shows a cross-section viewalong the line III-III of FIG. 3 in which the closed cells are squareshaped. Another commonly used closed polygonal transistor cell ishexagonal shaped, a cross-section view of which would again be as shownin FIG. 1. FIGS. 2 and 3 show the active cell area dimensions of thetransistor cells for both the open-cell and closed-cell geometries whichare the trench width T, the semiconductor mesa width M between trenchesand the cell pitch P which is the sum of T and M.

A desirable property for power transistors is to have good switchingperformance, that is fast switching and low switching losses when thedevice is turned on and turned off. This is particularly important wherethe power transistor is to be used in the output stage of a powersupply, for example a voltage regulation module (VRM), where it iscontinuously turned on and off at very high frequency. This goodswitching performance depends particularly on the device having a lowgate-drain capacitance. A limitation in this respect for the trench-gatedevice is the contribution to gate-drain capacitance added by the gateinsulation at the bottom of the trench. The possibility of reducing thedevice gate-drain capacitance by increasing the thickness of the trenchbottom insulation is known, for example from U.S. Pat. No. 4,992,390 andfrom WO-A-2003/043089 (our reference PHNL020937), and FIG. 1 of theaccompanying drawings shows that, for this purpose, the silicon oxidegate insulation 21B at the trench bottom is thicker than the siliconoxide gate insulation 21A at the trench sidewalls.

Methods are known for manufacturing trench-gate devices as indicatedabove with thicker gate insulation at the trench bottoms. U.S. Pat. No.6,291,298 proposes directional deposition of more silicon oxide at thebottom of the trench than on the sidewalls, and alternatively proposesdeposition of polysilicon in the trench which is then etched back toleave a portion at the bottom of the trench which portion is thenoxidised. U.S. Pat. No. 6,444,528 proposes forming a second trench atthe bottom of the trench and growing selective oxide in the secondtrench to form the thicker bottom gate insulation. We consider thatthere is a need for a further, different, method for manufacturingtrench-gate devices with thicker gate insulation at the trench bottoms.

According to the present invention there is provided a method ofmanufacturing a trench-gate silicon semiconductor device, the methodincluding forming trenches in a semiconductor body in an activetransistor cell area of the device, the trenches each having a trenchbottom and trench sidewalls, and providing silicon oxide gate insulationin the trenches such that the gate insulation at the trench bottoms isthicker than the gate insulation at the trench sidewalls, wherein themethod includes, after forming the trenches, the steps of:

(a) forming a silicon oxide layer at the trench bottoms and trenchsidewalls;

(b) depositing a layer of doped polysilicon adjacent the trench bottomsand trench side walls;

(c) forming silicon nitride spacers on the doped polysilicon adjacentthe trench sidewalls leaving the doped, polysilicon exposed at thetrench bottoms;

(d) thermally oxidising the exposed doped polysilicon to grow saidthicker gate insulation at the trench bottoms;

(e) removing the silicon nitride spacers; and

(f) providing gate conductive material within the trenches.

In a first embodiment of the invention step (b) deposits the layer ofdoped polysilicon on the silicon oxide layer formed in step (a), andstep (d) grows the thicker gate insulation below the nitride spacers.

A second embodiment of the invention includes the further step (g) offorming a silicon nitride layer at the trench bottoms and trenchsidewalls on the silicon oxide layer which has been formed in step (a),wherein step (b) deposits the layer of doped polysilicon on the siliconnitride layer formed in step (g) such that the silicon nitride layer atthe trench bottoms limits the downward growth of the thicker gateinsulation in step (d), and wherein the silicon nitride layer is removedfrom the trench sidewalls before depositing gate conductive material instep (f).

One important advantage of the method of the present invention is thatthe final thickness of the thicker silicon oxide gate insulation at thetrench bottoms is well controlled by the thickness of the layer of dopedpolysilicon deposited in step (b), and then exposed in step (c) takinginto account the oxidation time and temperature in step (d). In thefirst embodiment the oxidation process can be controlled so that afterthe bottom exposed doped polysilicon has been oxidised then only a smallamount of the silicon under the trench bottom is oxidised. In the secondembodiment the downward oxidation growth of the thicker gate insulationis completely controlled by the silicon nitride layer at the trenchbottom. In comparison with the method according to the presentinvention, the prior art proposal for directional deposition of siliconoxide at the bottom of the trench is difficult to achieve as well as tocontrol, in the prior art proposal to deposit polysilicon and then etchit back before oxidation it is difficult to control the etch back toproduce a required thickness, and the prior art proposal to form asecond trench in which the thicker bottom gate insulation is formed is acomplex method.

Another important advantage of the method of the present invention liesin the use of doped polysilicon rather than undoped polysilicon for thelayer which is deposited in step (b) and then thermally oxidised in step(d). Doped polysilicon oxidises faster than undoped silicon andtherefore lower temperatures and shorter oxidation times can be usedwhich reduces the thermal budget of the process and lessens the risk ofthis oxidation causing unwanted diffusion of the substrate doping of thedevice and also unwanted diffusion of implantations which may be presentin the device at that stage such as the channel accommodating bodyregion (23 as shown in FIG. 1). In particular, highly doped polysiliconoxidises much faster than undoped polysilicon at low temperatures.

In the method of present invention the doped polysilicon deposited instep (b) is preferably greater than 5 e 19 cm-3 As or P dopedpolysilicon, and furthermore in step (d) the doped polysilicon isthermally oxidised preferably at a temperature in the range 650-850° C.,in particular 700-800° C. For polysilicon doped to this level theoxidation time can be reduced by a factor of 10 at these lowtemperatures compared with the oxidation time for undoped polysilicon.

According to the present invention there is also provided a trench-gatesemiconductor device manufactured by the method as specified above.

An embodiment of a device in accordance with the present invention maybe defined as a trench MOSFET comprising:

a drain region of first conductivity type;

a body region over the drain region;

a trench extending from a first major surface through the body region;

source regions laterally adjacent to the trench at the first majorsurface;

thermal gate oxide on the side walls of the trench;

a gate electrode in the trench insulated from the body region by thegate oxide;

and a thick oxide plug formed of oxidised doped polysilicon at the baseof the trench extending into the drain region.

As explained above, the present invention is primarily directed toreducing the contribution to gate-drain capacitance added by the gateinsulation at the bottom of the trench in a trench-gate device,particularly bearing in mind the desirable property of good switchingperformance for power transistors. Another desirable property for powertransistors is to have a low specific on-state resistance. For low andmedium voltage power transistors, that is with a drain-source breakdownreverse voltage of up to respectively about 50 volts and about 200volts, the specific on-state resistance of the device is to a largeextent dependent on the sum total of the conducting channel peripheries.Thus for a given size of the device, that is a given active transistorcell area, a larger number of transistor cells in that active area leadsto a lower specific on-state resistance. For a given size of device atrench-gate structure vertical MOSFET device can have more transistorcells and a lower specific on-state resistance than a double diffusedplanar gate vertical MOSFET device (VDMOS).

For low and medium voltage trench-gate vertical power transistors, bothopen cell type and closed cell type, the number of cells in the activedevice area is made larger primarily by decreasing the cell pitch (P asshown in FIGS. 2 and 3). A disadvantage of doing this is that the amountof trenches in a given area increases and thus the gate-draincapacitance increases since this is partly determined by the trenchbottom area. This disadvantage becomes particularly important forcurrently proposed devices in which the cell pitch is less than 2micron, for example 1 micron, and it is difficult to achieve the targetlow gate-drain capacitance for these devices. The reduction ofgate-drain capacitance by providing thicker gate insulation at thetrench bottoms using the method of the present invention is thereforeparticularly advantageous for devices having the currently proposedsmall cell pitch as just mentioned.

In the case where a vertical power transistor manufactured by the methodof the present invention is a closed cell device, it may be defined ashaving a trench network which includes segment trench regions adjacentsides of the transistor cells, wherein said trenches in which the gateinsulation is thicker at said trench bottoms than the gate insulation atsaid trench sidewalls comprise the segment trench regions. Referringback to FIG. 3 of the accompanying drawings which shows the justspecified segment trench regions G2S and intersection trench regions G2Iadjacent corners of the cells it will be appreciated that, for a giventhickness, gate insulation at the bottom of the segment trench regionscontributes more to the gate-drain capacitance of the device than gateinsulation at the bottom of the intersection trench regions. Thus in thedevice as just defined the trenches in which the gate insulation isthicker at said trench bottoms includes the segment trench regions, andthese trenches optionally may also include the intersection trenchregions.

The above-defined first and second embodiments of the method of thepresent invention will now be described in detail with reference to theaccompanying drawings, in which:

FIG. 1 shows a schematic cross-section view of a known trench-gateMOSFET as has been described above;

FIG. 2 shows a plan view of an open cell geometry with the line II-IIindicating the cross-section of FIG. 1;

FIG. 3 shows a plan view of a closed square cell geometry with the lineIII-III indicating the cross-section of FIG. 1;

FIG. 4A to 4D show steps in a method of manufacturing a trench-gatesemiconductor device according to a first embodiment of the presentinvention; and

FIGS. 5A to 5D show steps in a method of manufacturing a trench-gatesemiconductor device according to a second embodiment of the presentinvention.

FIGS. 4A to 4D show steps in a method of manufacturing a trench-gatesemiconductor device according to a first embodiment of the presentinvention.

Referring now to FIG. 4A, a monocrystalline silicon semiconductor body10 with top and bottom major surfaces 10 a and 10 b is formed with an n+type drain region substrate 11 on which is grown an epitaxial n typedrain drift region 12. A p type channel-accommodating body region 23 maythen formed by implantation and diffusion into the drain drift region 12or by epitaxial growth on top of the drift region 12. N+ type regionsproviding source regions 24 for transistor cells to the sides oftrenches 20 are preferably implanted after the process steps shown inFIGS. 4A to 4D and are therefore shown with dotted lines. The regionsand their reference signs just referred to correspond to the referencedregions of the known device already shown in and described withreference to FIG. 1. Trenches 20, one of which is shown in FIG. 4A, arethen etched from the top major surface 10 a through the p body region 23and into the drain drift region 12. A layer of silicon dioxide 21 isthen deposited or grown, preferably grown, on the top surface 10 a andon the side walls and bottom of each trench 20.

Referring now to FIG. 4B, a layer 31 of doped polysilicon is thendeposited on top of the silicon body and adjacent the trench bottoms andsidewalls, that is in this embodiment directly on to the silicon oxidelayer 21. The polysilicon layer 31 is preferably highly doped, that isgreater than 5 e 19 cm-3, e.g. 1 e 20 cm-3, As or P doped. The thicknessof the doped polysilicon layer 31 is chosen to provide an oxidisedlayer, as will be described with reference to FIG. 4C, of approximatelydouble thickness and is initially for example 100 nm. A relatively thin,e.g. 20 nm, layer of silicon nitride is then deposited andanisotropically etched to form silicon nitride spacers 32 on the dopedpolysilicon 31 adjacent the trench sidewalls leaving the dopedpolysilicon exposed at the trench bottoms.

Referring now to FIG. 4C, the exposed doped polysilicon is thenthermally oxidised to grow thicker silicon dioxide 33 at the top of thebody 10 and, as gate-drain insulation, at the trench bottoms below thenitride spacers 32. During this step, the nitride spacers 32 protect thepolysilicon layer 31 and the silicon dioxide layer 21 at the side wallsof the trenches from oxidation and thickening. This step of thermaloxidation is preferably a wet oxidation at a temperature in the range650-850° C., preferably 700-800° C.

The final thickness, for example 200 nm, of the thicker silicon dioxideinsulation 33 at the trench bottoms is well controlled by the thicknessof the initial layer 31 of doped polysilicon deposited and then exposedas described with reference to FIG. 4B taking into account the oxidationtime and temperature. The oxidation process can be controlled so thatafter the bottom exposed doped polysilicon has been oxidised then only asmall amount of the silicon under the trench bottom is oxidised. Forpolysilicon doped to the level indicated, the oxidation time at thetemperatures indicated may be reduced by a factor of 10 compared withthe oxidation time which would be required for undoped silicon. Thisreduction in the thermal budget lessens the risk of this oxidationcausing unwanted diffusion of the substrate 12 doping and also unwanteddiffusion of the p body 23 (if already implanted) present in the deviceat that stage.

Referring now to FIG. 4D, the nitride spacers 32 are then removed, forexample with a wet etch, and then the trenches are filled with depositedor grown gate conductive material 34, for example doped polysilicon. Thethicker gate insulation 33 at the trench bottoms provides the thickergate insulation 21B as shown in FIG. 1, and the silicon dioxide 21initially grown as described with reference to FIG. 4A is retained asthe trench side wall gate insulation 21A as shown in FIG. 1. The dopedpolysilicon layer 31 at the sidewalls of the trenches which wasprotected from oxidation by the nitride spacers 32 can be left so as toform, together with the conductive material 34, a gate electrode for thedevice. In an alternative method, the silicon dioxide 21 at the trenchside walls as shown in FIG. 4D can be a sacrificial oxide which, afterremoval of the layer 31 from the trench sidewalls, is removed with a wetetch which will leave most of the thicker silicon oxide gate insulation33 at the trench bottoms, and then silicon oxide gate insulation can begrown at the trench side walls. This alternative needs more processsteps, and so is not preferred. The oxide 33 on the top surface 10a ofthe device is removed or etched back later in the process of making thedevice which includes providing, as shown in FIG. 1, the insulatingregion 25 over the gate conductive material 34 (22 as shown in FIG. 1),the source region 24 implantation and diffusion (preceded by the p body23 implantation and diffusion if the p body has not previously beenimplanted), the source metallisation 18, a gate connection and the drainmetallisation 19.

FIGS. 5A to 5D show steps in a method of manufacturing a trench-gatesemiconductor device according to a second embodiment of the presentinvention.

Referring now to FIG. 5A, a silicon semiconductor body 10 with a drainregion substrate 11, a drain drift region 12, a p body region 23, atrench 20 and a layer of silicon dioxide 21 is formed in the same manneras has been described above with reference to FIG. 3A. A silicon nitridelayer 41 is also formed at the trench bottoms, the trench side walls andthe top of the body 10 on the silicon oxide layer 21.

Referring now to FIG. 5B, a layer of doped polysilicon 31 and nitridespacers 32 are formed in the same manner as has been described abovewith reference to FIG. 4B but in this case on the nitride layer 41. Thedoped polysilicon layer 31 is exposed at the trench bottom, but with thenitride layer 41 between the exposed doped polysilicon layer 31 and thesilicon dioxide layer 21 at the trench bottom.

Referring now to FIG. 5C, the exposed doped polysilicon layer 31 isthermally oxidised in the same manner as has been described above withreference to FIG. 4C but in this case the silicon nitride layer 41 atthe trench bottoms limits the downward growth of the thicker silicondioxide gate insulation 33 at the trench bottoms.

Referring now to FIG. 5D, the silicon nitride spacers 32, the dopedpolysilicon layer 31 and the silicon nitride layer 41 at the sidewallsof the trenches are removed. The silicon dioxide 21 may be retained asthe trench sidewall gate insulation, as is shown in FIG. 5D, or it maybe a sacrificial oxide which is removed before growing silicon oxidegate insulation at the trench sidewalls. The trenches are then filledwith deposited or grown gate conductive material 34 to form a gateelectrode for the device. In this case the silicon nitride layer 41 willbe left in the bottom of the trenches and on top of the body 10. Thiswill not do any harm to the device performance.

From reading the present disclosure, other variations and modificationswill be apparent to persons skilled in the art. Such variations andmodifications may involve equivalent and other features which arealready known in the art, and which may be used instead of or inaddition to features already described herein.

Although Claims have been formulated in this Application to particularcombinations of features, it should be understood that the scope of thedisclosure of the present invention also includes any novel feature orany novel combination of features disclosed herein either explicitly orimplicitly or any generalisation thereof, whether or not it relates tothe same invention as presently claimed in any Claim and whether or notit mitigates any or all of the same technical problems as does thepresent invention.

Features which are described in the context of separate embodiments mayalso be provided in combination in a single embodiment. Conversely,various features which are, for brevity, described in the context of asingle embodiment, may also be provided separately or in any suitablesubcombination. The Applicants hereby give notice that new Claims may beformulated to such features and/or combinations of such features duringthe prosecution of the present Application or of any further Applicationderived therefrom.

1. A method of manufacturing a trench-gate silicon semiconductor device(1), the method including forming trenches (20) in a semiconductor body(10) in an active transistor cell area of the device, the trenches (20)each having a trench bottom and trench sidewalls, and providing siliconoxide gate insulation (21A, 21B) in the trenches such that the gateinsulation (21B, 33) at the trench bottoms is thicker than the gateinsulation (21A, 21) at the trench sidewalls, wherein the methodincludes, after forming the trenches (20), the steps of: forming asilicon oxide layer (21) at the trench bottoms and trench sidewalls;depositing a layer of doped polysilicon (31) adjacent the trench bottomsand trench side walls; forming silicon nitride spacers (32) on the dopedpolysilicon (21) adjacent the trench sidewalls leaving the dopedpolysilicon exposed at the trench bottoms; thermally oxidising theexposed doped polysilicon to grow said thicker gate insulation (33) atthe trench bottoms; removing the silicon nitride spacers (32); andproviding gate conductive material (34) within the trenches.
 2. A methodas claimed in claim 1, wherein step (b) deposits the layer of dopedpolysilicon (31) on the silicon oxide layer (21) formed in step (a), andwherein step (d) grows the thicker gate insulation (33) below thenitride spacers (32).
 3. A method as claimed in claim 1, including thefurther step (g) of forming a silicon nitride layer (41) at the trenchbottoms and trench sidewalls on the silicon oxide layer (21) which hasbeen formed in step (a), wherein step (b) deposits the layer of dopedpolysilicon (31) on the silicon nitride layer (41) formed in step (g)such that the silicon nitride layer (41) at the trench bottoms limitsthe downward growth of the thicker gate insulation (33) in step (d), andwherein the silicon nitride layer (41) is removed from the trenchsidewalls before depositing gate conductive material (34) in step (f).4. A method as claimed in claim 1, wherein the silicon oxide layer (21)formed at the trench sidewalls in step (a) is retained as trenchsidewall gate insulation (21A) before depositing gate conductivematerial (34) in step (f).
 5. A method as claimed in claim 1, whereinthe doped polysilicon (31) deposited in step (b) is greater than 5 e 19cm-3 As or P doped polysilicon.
 6. A method as claimed claim 1, whereinin step (d) the doped polysilicon (31) is thermally oxidised at atemperature in the range 650-850° C.
 7. A method as claimed in claim 6,wherein the oxidation temperature range is 700-800° C.
 8. A trench-gatesilicon semiconductor device (1) manufactured by the method as claimedclaim
 1. 9. A device as claimed in claim 8, wherein the device is avertical power transistor.
 10. A device as claimed in claim 9, whereinthe transistor cells have a cell pitch less than 2 micron.
 11. A deviceas claimed in claim 9, wherein the device (1) has a plurality ofelectrically parallel closed transistor cells (TC2) configured in atwo-dimensionally repetitive pattern in the active area of the device,wherein a trench network includes segment trench regions (G2S) adjacentsides of the transistor cells (TC2), and wherein said trenches (20) inwhich the gate insulation is thicker (21B, 33) at said trench bottomsthan the gate insulation at said trench sidewalls (21A, 21) comprise thesegment trench regions (G2S).
 12. A method of manufacturing atrench-gate silicon semiconductor device substantially as hereindescribed with reference to and as shown in FIGS. 1, 2, 3, and 4A to 4Dof the accompanying drawings.
 13. A method of manufacturing atrench-gate silicon semiconductor device substantially as hereindescribed with reference to and as shown in FIGS. 1, 2, 3, and 4A to 4D,as modified by FIGS. 5A to 5D, of the accompanying drawings.